Embodiments of the present invention relate to a semiconductor memory device and a method of operating the same, more particularly relate to a semiconductor memory device having a charge trap type memory cell and a method of operating the same.
A non-volatile memory device of a semiconductor memory device has characteristics that data is not erased even though a power is not supplied. A charge trap type flash memory device of the non-volatile memory device stores data by using a memory cell where a tunnel dielectric layer, a charge trap layer, a blocking dielectric layer and a gate conductive layer are laminated on a semiconductor substrate. The charge trap type flash memory device charges electric charges in the charge trap layer in case that a high voltage is supplied to a gate of the memory cell in a program operation. A threshold voltage of the memory cell varied depending on amount of the electric charges charged in the charge trap layer is detected in a read operation, and the stored data is determined based on level of the detected threshold voltage.
The memory cell in the non-volatile memory device is a device that may perform a program operation/an erase operation, and the program operation and the erase operation are performed by changing the threshold voltage of the memory cell.
FIG. 1 is a flowchart illustrating an erase operation of a conventional semiconductor memory device.
In FIG. 1, a semiconductor memory device performs the erase operation that uses an incremental step pulse erase ISPE method.
Particularly, an erase voltage is supplied to a p-well of a semiconductor substrate on which memory cells are formed in step S1. Subsequently, an erase verification operation is performed for verifying whether or not threshold voltage of every memory cell is less than a target threshold voltage in steps S2 and S3. In case that it is verified that the threshold voltage of every memory cell is less than the target threshold voltage, it is determined that an erase operation is passed, and thus, the erase operation is finished. In case that it is verified that threshold voltage of one or more memory cell is higher than the target threshold voltage, it is determined that the erase operation is failed. In case that it is determined through the erase verifying operation that the erase operation is failed, a voltage increased by step voltage from an erase voltage supplied in previous operation of supplying the erase voltage is set to new erase voltage in step S4. The step S1 and following steps are performed again by using the new erase voltage.
FIG. 2 is view illustrating a graph for showing change of threshold voltage in an erase operation of a conventional semiconductor memory device.
In FIG. 2, the erase operation using the ISPE method is performed by repeating an erase loop (the steps S1 to S4), and so the erase voltage increased step-by-step is supplied to the p-well of the semiconductor substrate. However, a back tunneling phenomenon occurs through a blocking dielectric layer in case that the erase voltage increases to a voltage more than constant voltage in the charge trap type memory cell, and thus, the threshold voltage of the memory cell may increase again. For example, the threshold voltage of the memory cell lowers gradually in case that the erase voltage is supplied in sequence to A, A+1, A+2, but the threshold voltage of the memory cell may increase due to the back tunneling phenomenon through the blocking dielectric layer in case that the erase voltage boosts to A+3.
Accordingly, threshold voltage distribution of the memory cell may lack uniformity even though the erase loop is performed repeatedly using the ISPE method, and the erase operation may fail because the threshold voltage of the memory cell is not erased to a voltage less than the target threshold voltage.